1. Field of the Invention
The present invention relates to a differential signal interfacing device and related method, and more particularly to a reduced swing differential signaling (RSDS) interfacing device and related method.
2. Description of the Prior Art
In the existing driving circuits of display devices, a Reduced Swing Differential Signal (RSDS) interface is commonly used transmission interface. A typical driving circuit includes a timing controller and source drivers. The timing controller utilizes a number of transmission line pairs to transmit RSDS signals to the source drivers in a bus manner. Each RSDS signal corresponds to a transmission line pair and can be defined into one signal type. In general, the RSDS signal for one transmission line pair is defined as a clock signal and the RSDS signals for the rest of the transmission line pairs are defined as data signals, each representing one-bit data.
Please refer to FIG. 1, which is a schematic diagram of a display device 10 according to the prior art. The display device 10 includes a timing controller TCON_PA and source drivers SD_PA1-SD_PAm. The timing controller TCON_PA uses the RSDS interface, and thereby transmits a data signal DATA_PA with a transmission line pair L1 and a clock signal CLK with a transmission line pair L2. Furthermore, the timing controller TCON_PA transmits a start-up signal DIO to the source drivers SD_PA1 with a transistor-to-transistor logic (TTL) signaling interface. The source drivers SD_PA1-SD_Pam transmit the start-up signal DIO in a cascading manner. That is, the source drivers SD_PA2-SD_Pa(m−1) delay the start-up signal DIO and thereby generate start-up signals DIO2-DIO(m−1) for the following source driver.
When the display device 10 prepares to output an image frame to its panel, the timing controller TCON_PA transmits the start-up signal DIO to the source drivers SD_PA1. Subsequently, the source drivers SD_PA1 waits a predefined time and then derives the data signal DATA_PA from the transmission line pair L1. And then, the source driver SD_PA1 outputs the start-up signal DIO2 to the following source driver SD_PA2. When receiving the start-up signal DIO2 from the source driver SD_PA1, the source driver SD_PA2 performs the same operations as the source driver SD_PA1 does, waiting a predefined time and then deriving the data signal DATA_PA from the transmission line pair L1. The source drivers SD_PA3-SD_PAm also operate in the same way. In the end, the timing controller TCON_PA can transfer all data of the image frame to the source drivers SD_PA1-SD_PAm.
Please refer to FIG. 2, which is a schematic diagram of signal waveforms of the display device 10. FIG. 2 only depicts partial waveforms for simplicity. From top to bottom, the shown waveforms are the clock signal CLK, the start-up signal DIO, the start-up signal DIO2, the start-up signal D103 and the data signal DATA_PA. The data signal DATA_PA includes signal intervals SD_PA_DATA1 and SD_PA_DATA2, which are valid intervals for the source drivers SD_PA1 and SD_PA2 respectively to derive data, and other intervals are omitted here. The obliquely lined interval of the data signal DATA_PA means that no RSDS signals are outputted from the timing controller TCON_PA. In FIG. 2, the signal intervals SD_PA_DATA1 and SD_PA_DATA2 lag behind the start-up signals DIO and DIO2 for a predefined time, respectively. The relationship between the data signal intervals and associated start-up signals allows the source drivers SD_PA1 and SD_PA2 to derive data successfully.
However, the start-up signals DIO1-DIO(m−1) are easily affected by noise due to their TTL signal form. In addition, since the clock signal CLK is a differential signal, the skew between the start-up signals DIO1-DIO(m−1) and the clock signal CLK is difficult to control. Furthermore, the start-up signals DIO1-DIO(m−2) must be delayed in the source drivers for less than a clock cycle of the clock signal CLK, so that any of the source drivers will not be triggered to derive data at the wrong times. In this situation, the start-up signals DIO1-DIO(m−2) have to be delayed for a shorter time in the source drivers as the clock signal CLK is increased in frequency. Therefore, the delays of the start-up signals DIO1-DIO(m−2) and the system clock rate become a trade-off under guarantee of correct timings used for the source drivers to derive the image data.